The present invention relates to semiconductor packages, and more particularly to a semiconductor package, in which a semiconductor chip is mounted in a flip chip manner on a lead frame.
A semiconductor device tends to be made in low cost, high performance and high integration, and is also preferably dimensioned with reduction in size and overall thickness thereof, in correspondence to a trend of low-profile electronic products. A QFN (quad-flat non-leaded) semiconductor package is a mainstream conventional product, due to advantages in that the QFN semiconductor package is only slightly larger in dimension than a semiconductor chip mounted therein, and is cost-effectively made in a lead frame based batch manner.
For fabricating such a QFN semiconductor package, generally it is first to mount at least one semiconductor chip on a lead frame having a die pad and a plurality of leads; then, a plurality of gold wires are bonded for electrically connecting the chip and the leads; and finally, an encapsulant is formed to encapsulate the chip. However, in the wire bonding process, due to dense distribution of the leads or complicated layout of the chip, wire loops of the gold wires are interlaced, and thus electric interference occurs if the adjacent gold wires are not properly spaced from each other. Moreover, during the formation of the encapsulating, the gold wires with relatively longer wire loops usually cannot sustain impact from mold flow, and therefore encounter problems such as wire sweep or even short circuit if coming into contact with one another.
In addition, with the development in fabrication for a flip chip semiconductor package, a technique of reflowing solder bumps onto bonding pads for establishing electrical connection is getting more commonly used. Comparing to the conventional wire bonding process, the implantation of the solder bumps is implemented by using a one-step and self-alignment process, and thus is more cost-effective and less time-consuming. Accordingly, U.S. Pat. No. 5,677,567 titled as xe2x80x9cLeads Between Chips Assemblyxe2x80x9d discloses a flip chip on lead frame technology. As shown in FIG. 5, a semiconductor device 4 comprises a lead frame (not shown), which is made of a metallic material such as copper, and mainly consists of a plurality of leads 42 variable in length; a plurality of semiconductor chips 43 each having an active surface 430 disposed with a plurality of bonding pads thereon, and a non-active surface 431; a plurality of solder bumps 44 implanted on the bonding pads 432, allowing the leads 42 to be reflowed on each of front and back surfaces thereof with one of the chips 43 in a manner that the active surface 430 of the chip 43 faces the leads 42; and an encapsulant 45 formed on the leads 42 for encapsulating the semiconductor chips 43.
This technology is therefore characterized in that the semiconductor chip 43 is bonded and electrically connected to the corresponding leads 42 in a flip-chip manner. The solder bumps 44 are made of tin/lead alloy (generally in composition of tin 63/lead 37 alloy which gives a soft characteristic). As such, during the reflow process, as temperature raises to a certain degree, the solder bumps 44 collapse to become instantly eutectic with contact regions 421 of the leads 42. This therefore makes an intermetallic compound layer (not shown) formed between the solder bumps 44 and the contact regions 421, in an effort to firmly reinforce the bonding between the solder bumps 44 and the leads 42. The formation of the intermetallic compound is called a wetting process. However, due to good wetability of the copper-made lead frame (not shown), after the solder bumps 44 are bonded to predetermined positions (i.e. the contact regions 421) on the leads 42 of the lead frame, the solder bumps 44 still keep collapsing and extending outwardly to be spread on the leads 42, as illustrated in FIG. 6. This over-collapsing of the solder bumps 44 increases in brittleness of the bonding between the solder bumps 44 and the leads 42, thereby easily resulting in bonding structural cracking or even loss of electrical properties. Further, the excessively deformed solder bumps 44 also lead to significantly decrease in the height difference between the semiconductor chip and the leads, and this detrimentally affects the implementation of subsequent processes in fabrication.
In order to solve the above-described problems, as shown in FIG. 7, U.S. Pat. No. 6,060,769 titled as xe2x80x9cFlip Chip on Leads Devicexe2x80x9d discloses a technology of forming a solder mask 47 on predetermined positions of the leads 42, wherein the solder mask 47 has at least one opening 470 with predetermined size for bonding the solder bumps 44 thereto. This technology in essence is to utilize the opening size S of the solder mask 47 for controlling the collapse degree of the solder bumps 44. As the size S of the opening 470 increases, the solder bumps 44 can extend outwardly to a greater extent; that is, the larger the collapse degree, the smaller the vertical height h of the solder bumps 44 correspondingly. Therefore, with the control in the collapse degree of the solder bumps 44, the height difference between the semiconductor chip 43 and the leads 42 can be predetermined, thus eliminating the occurrence of the over-collapsing of the solder bumps 44.
However, the formation of the solder mask on the lead frame employs such as screen printing or photo-lithographic patterning processes, which are quite complex and ineffective in cost, therefore making it difficult to widely implement in practice. In the case of the solder bumps being alternatively made of e.g. tin 5/lead 95 alloy for raising a melting point thereof, allowing the over-collapsing of the solder bumps to be prevented from occurrence, however, such solder bumps generally doubles up the manufacturing cost thereof
A primary objective of the present invention is to provide a lead frame and a semiconductor package with the lead frame, in which a die pad is elevated in position with a proper height difference relative to leads, so as to prevent solder bumps from over-collapsing in a die bonding process, and thus assure bonding reliability of the solder bumps in the semiconductor package.
Another objective of the invention is to provide a lead frame and a semiconductor package with the lead frame, in which a lead frame good in heat dissipation is employed, allowing heat generated from a semiconductor chip to be quickly dissipated through a die pad of the lead frame after the semiconductor chip is attached to the die pad, so as to improve overall heat dissipating efficiency of the semiconductor package.
In accordance with the foregoing and other objectives, a semiconductor package proposed in the present invention comprises: a lead frame made of metal such as copper, and having a die pad and a plurality of leads, wherein the die pad is higher in elevation than the leads, and a height difference formed between the die pad and the leads does not exceed a height of a plurality of solder bumps, and further a plurality of contact portions are pre-defined on the leads for bonding the corresponding solder bumps thereto; a non-conductive thermal adhesive applied on a top surface of the die pad, for adhering a semiconductor chip to the die pad; at least one semiconductor chip attached in a flip chip manner to the contact portions of the leads via the solder bumps; and an encapsulant for encapsulating the semiconductor chip on the lead frame.
In a reflow process for heating the foregoing semiconductor package to a certain temperature, the soft solder bumps having a low melting point start to melt and collapse. Due to good wetability of the copper-made lead frame, the solder bumps keep collapsing, making the semiconductor chip move downwardly due to gravity of its weight. When the semiconductor chip descends in elevation to abut the non-conductive thermal adhesive, the die pad stops the chip from moving, thereby forcing the solder bumps to stop collapsing to be maintained with a certain height.
With the provision of the height difference between the die pad and the leads for controlling collapse degree of the solder bumps, it is also beneficial for implementing subsequent processes since the chip is properly spaced from the leads. Moreover, as the die pad functions to restrain the solder bumps from keeping collapsing, it eliminates the occurrence of over-collapsing of the solder bumps and bonding brittleness between the solder bumps and the lead frame, so that structural strength and electrical properties can be assured in the semiconductor package.